CMOS technology has been continuously optimized for scaled-down devices to improve performance and high-level integration. Frequently, the optimizations are accompanied by an increase in the number of steps, resulting in a more complicated and costly product. Moreover, as the feature size of devices scale down, it is important to prevent punch-through between source and drain regions and between adjacent devices under the field oxide regions. Many different techniques have been employed in order to suppress punchthrough from occurring, including forming shallow junctions. Howvever, shallow junctions are characterized by reduced source/drain implant doses that invariably cause the resistivity to increase.
The lithography in CMOS devices is considered to be the most expensive portion of the fabrication process. Lithography is also considered a bottleneck for throughput purposes as well. Typically, the prior art draws on additional steps to decrease cost or to reduce the number of masks required. For example, steps such as the number of implants, critical masking or critical etching are often increased to reduce cost or the number masks used in the fabrication of CMOS devices.